`include "ex.vh"

`define CSR_SIG_wid 81
    `define CSR_SIG_RE 80
    `define CSR_SIG_WE 79
    `define CSR_SIG_NEED_MASK 78
    /*  
        csr_re              1
        csr_we              1
        csr_need_mask       1
        csr_num             14
        csr_wvalue          32
        csr_wmask           32      //exp12: add 81 bit
    */
`define EX_SIG_wid 4

`define fs_2_ds_bus_wid 64 + 1 + `EX_SIG_wid
/*fs_to_ds_bus = {
                    inst ,              32
                    pc,                 32   
                    ex
                    ex_signal
                };*/
`define ds_2_es_bus_wid 157+`CSR_SIG_wid+1+`EX_SIG_wid+1+2+5+5+1
/*ds_to_es_bus = {
                    refetch             1
                    invtlb_op            5
                    tlb指令             5
                    rdcntvl.w           1
                    rdcntvh.w           1
                    csr_signal,         81
                    ex,                 1
                    ex_signal,
                    ertn,               1
                    //157
                    alu_op,             12
                    mem_op,             4       //mem_op[3]: 1->ld, 0->st; mem_op[2]: 1->ld_w/h/b, 0->ld_hu/bu; 低二位:11->word, 10->half, 01->byte,   若为全0, 没有ld和st操作
                    gr_we,              1
                    dest,               5
				    rkd_value,          32
                    ds_pc,              32
                    alu_src1,           32
                    alu_src2,           32
                    inst_mul_w,         1
                    inst_mulh_w,        1
                    inst_mulh_wu,       1
                    inst_div_w,         1
                    inst_div_wu,        1
                    inst_mod_w,         1
                    inst_mod_wu         1
                }*/
`define es_2_ms_bus_wid 75+`CSR_SIG_wid+1+`EX_SIG_wid+1+3+1
/*es_to_ms_bus = {
                    refetch             1
                    除tlbsrch，invtlb之外的tlb指令 3
                    csr_signal,         81
                    ex,                 1
                    ex_signal,
                    ertn,               1
                    //75
                    es_ld_op,           3       //ld_op[2]: 1->ld_w/h/b, 0->ld_hu/bu; 低二位:11->word, 10->half, 01->byte,
                    es_vaddr2           2
                    es_alu_result,      32
                    es_gr_we,           1
                    es_dest,            5
                    es_pc               32
                }*/
`define ms_2_ws_bus_wid 70+`CSR_SIG_wid+1+`EX_SIG_wid+1+3+1
/*assign ms_to_ws_bus = {
                    refetch             1
                    之外的tlb指令         3
                    csr_signal,         81
                    ex,                 1
                    ex_signal,  
                    ertn,               1
                    //70
                    ms_gr_we,           1
                    ms_dest,            5
                    ms_final_result,    32
                    ms_pc               32
                };*/

